Microprocessors read and write binary values to and from memory in order to read data and execute computer software. Throughout the last several years of microprocessor design, two primary memory formats have been used to store binary information in external or internal memory. Processors using different formats have typically been incompatible with one another. One commonly-used data storage format is illustrated in FIG. 1 and is referred to as a big-endian format. A second commonly-used format is illustrated in FIG. 2 and is referred to as a little-endian format.
In FIG. 1, four byte memory locations are illustrated. The four memory locations may be used to store four bytes of information referred to as byte 0, byte 1, byte 2, and byte 3. In another form, the four storage locations in FIG. 1 may be used to store a halfword 0 and a halfword 1. Each halfword is a 16-bit value that comprises two bytes. In addition, the four storage locations in FIG. 1 may be used to store a word of data which is a 32-bit value. Therefore, the storage locations in FIG. 1 allow byte, halfword, and word storage of data. In another lingual convention used primarily for 16-bit bus machines, halfwords are referred to as 16-bit "words" and the 32-bit word in FIG. 1 is referred to as a "longword."
Byte storage does not vary significantly between a big-endian format and a little-endian format. Big-endian and little-endian, however, differ extensively when halfwords and words are stored. Referring to FIG. 1, halfword 0 is stored in two byte locations referred to as byte 0 and byte 1. Byte 0 is a most significant portion of the halfword and byte 1 is a least significant portion of the halfword. Byte 0 stores the value 12 in hexadecimal and byte 1 0 stores the value 34 in hexadecimal. Therefore, halfword 0 will be read from FIG. 1 as being a hexadecimal value 1234. In a similar manner, halfword 2 will be read from memory, having a most significant byte 56 and a least significant byte 78 so that halfword 1 stores the hexadecimal value 5678.
In FIG. 1, the byte 0 will have an address value less than byte 1, byte 1 will have an address value less than byte 2, and byte 2 will have an address value less than byte 3. For example, if byte 0 was located in memory such that byte 0 has an address of 50 hexadecimal, byte 1 will have an address of 51 hexadecimal, byte 2 will have an address of 52 hexadecimal, and byte 3 will have an address of 53 hexadecimal. Therefore, for example, byte 3 is referred to as residing in a higher address space than bytes 0, 1 or 2. Therefore, when reading halfwords or words from memory, most significant bytes in the big-endian format are stored in low address space whereas least significant byte portions are stored in a higher address space than the most significant bit portions.
When a 32-bit word is stored in FIG. 1, the value read will be 12345678 hexadecimal due to the fact that Byte 0 is a most significant byte and Byte 3 is a least significant byte.
FIG. 2 illustrates the little-endian data format. Halfword 0 of FIG. 2 will be read from memory as having a value of 5678. This is because, when using little-endian data storage format, most significant bytes are stored in a higher address space than least significant bytes. This little-endian format is the reverse of the big-endian format. Therefore, halfword 1 will be read as a value 1234. If a 32-bit word value referred to as word 0 is read from memory in FIG. 2, this word will have a hexadecimal value of 12345678.
In summary, if a 32-bit word is read from FIG. 1, that 32-bit value would be hexadecimal 12345678. Also, if a 32-bit word is read from FIG. 2 using the little-endian format, the hexadecimal value 12345678 is read. However, as one can easily see from FIGS. 1 and 2, even though both reads result in the same value, the individual bytes of FIG. 1 and FIG. 2 are reversed when compared to each other. This inherent reversal of byte order between the big-endian format and the little-endian format results in problems when a microprocessor must read both a big-endian format and a little-endian format.
One way in which the prior art has tried to read both the big-endian and the little-endian formats in memory has been to provide a special status bit internal to a CPU which identifies which type of data format is being accessed with each read instruction. This bit must be toggled every time the format of the data in memory changes. Using this technique, if a CPU is required to read a big-endian data value followed by a little-endian data value, these two reads would require at least four instructions. A first instruction that is a write instruction would be used to set the internal status bit to a value which allowed big-endian reads. A second instruction that is a read instruction would perform the big-endian read. A third instruction that is a write instruction would be used to change the internal status bit to indicate a little-endian read. Finally, a fourth instruction that is a read instruction would be used to actually read the little-endian data from memory.
Therefore, at least four instructions are needed to read two conflicting data formats stored consecutively in memory when using this status bit methodology.
In another form, a first opcode may be used to perform little endian operations and a second opcode may be used to perform big endian operations. This method involves more complicated instruction decode circuitry and is limiting since a programmer may not know which type of data is being accessed. In addition, code written for one data-type cannot be easily switched to another database.
A new method for reading both big-endian and little-endian formats from memory is needed in order to improve the performance of CPUs which are required to access both the big-endian format and the little-endian format .